IBM Flood Microprocessors
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IBM researchers, in collaboration with the Fraunhofer Institute in Berlin, have developed a rather unconventional way to keep microprocessors that are stacked on top of each other cool. The long running problem has now been solved by channelling water through the chips. Yes you heard that right.
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“As we package chips on top of each other to significantly speed a processor’s capability to process data, we have found that conventional coolers attached to the back of a chip don’t scale. In order to exploit the potential of high-performance 3-D chip stacking, we need interlayer cooling,” explained Thomas Brunschwiler, project leader at IBM’s Zurich Research Laboratory.
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“Until now, nobody has demonstrated viable solutions to this problem,” he added.
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IBM say that 3-D chip stacks have an aggregated heat dissipation of nearly 1 kilowatt, with an area of 4 square centimetres and a thickness of about 1 millimetre.
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IBM?s solution to the problem is to create many tiny channels, as thin a human hair for water to flow through between the chip stacks, getting the water extraordinarily close to the source of the heat.
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“This truly constitutes a breakthrough. With classic backside cooling, the stacking of two or more high-power density logic layers would be impossible,” noted Bruno Michel, manager of the chip cooling research efforts at the IBM Zurich Lab.
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The experiments involved scientists piping water through a square-centimetre test vehicle, consisting of a cooling layer between two dies, or heat sources. Packed with 10,000 vertical interconnects per square centimetre, the cooling layer measured only about 100 microns in height, IBM reported.
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IBM likened the complexity of the system to a human brain in that millions of nerves and neurons for signal transmissions are intermixed but do not interfere with tens of thousands of blood vessels for cooling and energy supply.
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The scientist drille holes through the layers for single transmission. To insulate these ?nerves?, scientists left a silicon wall around each interconnect - also called silicon vias - and added a fine layer of silicon oxide to provide insulation from the water. Each of the structures has to be fabricated to an accuracy of 10 microns - 10 times more accurate than for interconnects and metallizations in current chips.
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Michael Loughran, IBM communications manager for IBM Research said, “Having water cooling in between chip layers is a challenge since we have to make sure that the through-silicon vias are safely isolated from the water. We have developed a bonding technique that creates the electrical connection and at the same time provides a sealing ring,”
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In the final stage of the setup, the researchers placed the assembled stack in a silicon cooling container and pumped water through the chip layers.
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“We envisage this to hit the market with high volumes in about 10 years from now. In the meantime, we are seeking some niche applications to allow us to create a mature technology. [The] first niche applications will be around in five years,” Loughran said.
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